Silicon carbide (SIC) based metal oxide semiconductor field effect transistors (MOSFETs) offer significant advantages over their silicon (Si) based counterparts in high power applications. However, one advantage that Si-based MOSFETs have over SiC-based MOSFETs is the higher internal gate-source capacitance CGS. Having a higher CGS tends to keep the Si-based MOSFETs from erroneously turning on due to transients in drain bias. As such, there is a need for a space-efficient and effective technique for increasing the effective CGS for SiC-based MOSFETs.